CM2431 SAR ADC Differential input, 1.8MSPS sampling rate 20 bit

Overview
The CM2431 is a high-precision, high-speed, low-power, 20-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an integrated pre-charge input driver, operating from a single supply. It uses an externally provided reference voltage (VREF), which can be set independently of the supply voltage.

Power consumption of the CM2431 varies linearly with the sampling rate.

The pre-charge input driver reduces signal chain complexity and power consumption while supporting high channel density. With the pre-charge driver enabled, the low input current combined with a wide sampling window eliminates the need for a dedicated ADC driver, thereby simplifying external circuit design.

The input range compression mode of the CM2431 allows full ADC code range coverage without requiring a negative supply for the driver amplifier. Input overvoltage clamp circuitry protects the ADC inputs from overvoltage events, minimizes disturbance to the reference input, and removes the need for external protection diodes.

With a sampling rate of up to 1.8 MSPS, the CM2431 enables accurate capture of high-frequency signals and supports oversampling. The ADC's excellent linearity ensures high dynamic performance in oversampled systems. An independent logic supply (VIO) allows compatibility with 1.8 V, 2.5 V, 3 V, and 5 V logic interfaces.

The CM2431 is available in MSOP-10 and DFN-10 packages and is specified for operation from –40°C to +125°C.

Features

• Single supply voltage: 1.8 V
• Logic interface voltage: 1.71 V to 5.5 V
• Differential analog input range: ±VREF (VREF range: 2.4 V to 5.1 V)
• 20-bit resolution, no missing codes
• Sampling rate: 1.8 MSPS

Performance

• INL: ±4.5 ppm maximum
• Dynamic range: 105 dB (OSR = 2), 131 dB (OSR = 1024)
• SNR: 100.5 dB (fIN = 1 kHz, VREF = 5 V)
• SNDR: 100 dB (fIN = 1 kHz)
• THD: –120 dB (fIN = 1 kHz)
• Integrated pre-charge input driver
• Greatly reduced kickback, input current as low as 0.5 μA/MSPS
• Wide sampling window: nearly 50% of each conversion cycle allocated to sampling
• Valid data from first conversion with no pipeline delay
• Input range compression mode (suitable for single-supply operation)
• Input overvoltage clamp capable of sinking up to 50 mA
• SPI / QSPI / MICROWIRE-compatible serial interface
• Low power consumption:
  • 80 μW (10 kSPS, total power)
  • 13 mW (1.8 MSPS, total power)
• Package options: MSOP-10 (3 mm × 3 mm) and DFN-10 (3 mm × 3 mm)

DFN10